SECTION – 2
DIGITAL LOGIC CIRCUITS
Session
1
Ex 1: Design and implement the
Exclusive-OR gate using AND, OR and NOT gates.
Ans:
Step 1:
Circuit specification:-
Exclusive or is a combinational
circuit the Forms the ex-or operation on the two input values x and y.
Input: Two bits (A, B)
Output: Output= A (+) B
Step 2: Truth Table
Step 3: Minterm t= F1 (1, 2)
Step 4: Karnaugh maps
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Step5:
expression
Output = A (+) B
Step 6: Circuit
Ex
2: Design
an “Alarm circuit” using only OR gate in which, if ‘doors’ OR ‘windows’ Or
‘Fire alarm’ is activated and then alarm sound should start.
Ans:
Step1:
Specification
Alarm circuit is a combination circuit that
forms output a if ‘doors’ OR ‘windows’ Or ‘Fire alarm’ are activated by setting
the corresponding bit 1.
Input: 3 input bits
(‘d’,’w’,’f’)
Output: 1 bit
Step2: Truth table
Step 3: identifying
Minterms
Output= f+d+w
Step 4: K-map
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Step5: Expression
Output=
f+d+w
Step6: Circuit
Ex
3: We know NAND gate is universal gate
but we need proof, so Design other gates like OR, NOR, AND and NOT using only
NAND gates.
Ans:
(A)
NOT gate using NAND
(B)AND gate using NAND
(C) OR gate using
NAND
(D) NOR gate using
NAND
Ex
4: Design
a digital circuit whose output is equal to 1 if the majority of inputs are 1’s
. The output is 0 otherwise.
Ans:
Step1: Specification
Digital circuit whose output is equal
to 1 if the majority of inputs are 1’s The output is 0 otherwise.
Inputs: 4 bits (a, b, c, d)
Output: 1 bit
Step2: Truth Table
Step 3: Minterms
Output = F
(13, 14, 15)
Step4: K-map
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Step 5: expression
Output = abc+abd+bcd+acd
Step6: Circuit
Ex
5: Design the
following digital circuit
Ans:
1)
Half adder
A half
adder circuit takes 2 binary input and gives its sum. The input is 2 bits are a
and b the outputs are its sum and carry.
Step 1:
Specification
Inputs:
2 bits
Outputs:
Sum and Carry
Step2:
Circuit and Truth table
2)
Half Subtractor
A half
subtractor circuit takes 2 binary input and gives its difference. The input is
2 bits are a and b the outputs are its difference and borrow
Step 1:
Specification
Input:
2 bits
Output:
Difference and Borrow
Step 2: Circuit and Truth table
3)
Full Subtractor
A full
subtractor is a combinational circuit that performs a subtraction between two
bits taking into account that a one may be borrowed by a lower significant bit, the circuit has 3 inputs A, B and C. and 2
outputs Difference and Borrow.
Step1.
Specification
Inputs:
A, B and C
Outputs:
Difference and Borrow
Step2:
Circuit and truth table
Ex 7: Design a
combinational circuit that takes 3-bit number and the output of that circuit
should be the square of the input.
Ans:
Step1:
Specification
Square of
the number is a combinational circuit that can be obtained by taking 3 bits
inputs and 6 bit outputs.
Step 2: Truth
table
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Step 3: Identifying
Minterms
O1=F1 (6, 7)
O2=F2 (4, 5, 7)
O3=F3 (3, 5)
O4=F4 (2, 6)
O5=0
O6=F6 (1, 3, 5, 7)
The
Boolean functions for the three inputs and 6 outputs are derived as follows:-
For F1 (6, 7)
O1=AB
For F2 (4, 5, 7)
O2=AB`+AC
For F3 (3, 7)
O3=A`BC+AB`C
For F4 (2, 6)
O4=BC`
For F6 (1, 3, 5, 7)
O6=C
Step4: Circuit
Ex
8: Design a
combinational circuit where input is a 4 bit number and output is it’s 2’s
complement.
Ans: Step1:
Inputs= A, B, C, D
Output=Q1,
Q2, Q3, Q4 (2’s complement)
Step2:
Truth table
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Step3: K-map
Q1=A`D+A`C+A`BC`+AB`C`D`
Q2=BC`D`+B`D+B`C
Q3=C`D+CD`
Q4=D
Step 4: Circuit
Ex
9: Design an encoder circuit, which will
convert decimal number to binary.
Ans:
An encoder
is a circuit that encodes a particular input to a different format.
A Decimal to binary encoder constructed below
Truth
table:
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Q1=D8+D9
Q2=D4+D5+D6+D7
Q3=D2+D3+D6+D7
Q4=D1+D3+D5+D7+D9
Circuit:
Session
2
Ex
10: Design
Sequential Circuit of clocked RS flipflop with 4 NAND gates.
Ans:
The
circuit has R and S inputs and a clock input. This latch flip flop is activated
by a positive level on the clock
input.
If clock =
0, Output Q, Q`= Hold (nochange)
If clock =
1, R=0, S=1,Q=1 State = Set
If clock =1,
R=1, S=0, Q`=1 State= Reset
If clock
=1, R=0, S=0, State = Hold (no change)
Ex 11: Design Sequential Circuit
of Clocked D flip flop with AND and NOR gates.
Ans:
A D-type
latch is shown below.
The
advantage of this is the single D input.
The flip flop
takes the value at its D input whenever the clock pulse input is high it will
effectively “track’ the input levels as long as the clock input is high.
If the
clock input is zero, the state will be that of the last state the flipflop was
when it was high.
Ex
13: Design Linear Feed-back Shift Register.
Ans:
A shift
register with feedback consists of four flip-flops connected in a shift
register configuration and feedback from these four flip-flops to the
flip-flop’s inputs. This particular counter is started by setting 1 in X1 and
0s in X2, X3 and X4. The sequence of states is then
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Notice
that this sequence contains 15 of 16 possible 4 bit numbers that might be taken
by that might be taken by this circuit. This is a widely used sequence which
occurs in many instruments and has many uses in radar system, sonar system,
coding encryption boxes, etc.
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In
the counter table, the flip – flop names are first listed, flowed by the
starting states. Then the successive states taken are listed in order, and the
final line contains the state preceding the starting state.
Ex
14: Design
a logical circuit that will calculate the less than for 2 bits...
Ans:
Step: 1
specification
This
circuit compares two inputs of size 2- bits i.e. its range is (0-3) the output
will be 1 if A<B else0
Input: 2
input bits
1 bit for
A0
1 bit for
A1
1 bit for
B0
1 bit for
B1
Output: 1
bit (either 0 or 1)
Step2:
Truth table
Step 3:
Minterms and K-map
O1=F1
(1, 2, 3, 6, 7, 11)
Circuit:
Ex
15: Design a multiplexer
circuit that accepts N inputs and Outputs the value of one of those outputs.
Ans:
Multiplexing
means transmitting a large number of information units over a smaller number of
channels or lines. A digital multiplexer is a combination circuit that selects
binary info from one of the many input lines and directs it to a single output
line.
Circuit:
Ex
16: Design
a decoder that has m inputs and 2^m outputs.
Ans: A decoder
has the characteristic that for each possible 2^n input which can be taken by
the n input cells, the matrix will have a unique one of its 2^n output lines
selected.
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